This invention relates to a method for forming a passivation layer, and more particularly, to a method for forming a passivation layer using a polyimide layer as a mask.
A passivation layer seals the underlying device structures from contaminants and moisture and also serves as a scratch protection layer. In fabricating a memory cell, a passivation layer such as CVD PSG or plasma enhanced CVD silicon nitride is deposited over the entire surface of the wafer to protect the devices in the wafer. In general, it is desirable to form a thick passivation layer, since a thicker passivation layer will provide better protection.
As shown in FIG. 1A, a cross sectional view of a typical wafer with a memory cell is shown with a protruding fuse. The oxide layer 3 in the periphery area 4 on the silicon substrate is etched to form the fuse window 5. A poly fuse 7 is formed in the fuse window 5. A silicon dioxide layer 9 is formed in both the periphery area 4 and the bonding pad area 10. The silicon dioxide layer 9 is used as a buffer layer to prevent the metal layer 13 from directly contacting a subsequently formed silicon nitride layer.
The silicon dioxide layer 9 covers the metal layer 13 on the silicon substrate in the bonding pad area 10. By using a first photomask (not shown), a first photoresist layer 15 on the periphery area 4 and the bonding pad area 10 is developed. A portion of the silicon dioxide layer 9 in the fuse window 5 and on the metal layer 13 is removed using the developed first photoresist layer 15 as a mask.
Referring to FIG. 1B, the first photoresist layer 15 is removed and a silicon nitride layer 19 is formed. Thus, the exposed metal layer 13 in the bonding pad area 10 and the periphery area 4 are covered by the silicon nitride layer 19. Next, by utilizing a second photomask (not shown), a second photoresist layer 21 on the bonding pad area 10 and on the periphery area 4 is developed. Then a portion of the silicon nitride layer 19 underlying the metal layer 13 is exposed, and the exposed silicon nitride layer 19 is etched. The silicon nitride layer 19 is used as a passivation layer to protect the devices and the poly fuse 7 in the semiconductor wafer from moisture and containment.
Referring to FIG. 1C, the second photoresist layer 21 is removed and a polyimide layer 23 is formed on the bonding pad area 10 and the periphery area 4. Subsequently, a third photomask (not shown) is used to pattern the polyimide layer 23. Then a curing step is used to increase the density of the polyimide layer 23, shrinking the polyimide layer 23 to expose a portion of the fuse window 5 and a portion of metal layer 13. The cured polyimide layer 23 serves as further passivation to prevent the attack of the alpha particle.
The oxide layer, the silicon nitride layer, and the polyimide layer are all used to serve as the passivation layer of the semiconductor wafer. Therefore, it is necessary to use three photomasks to form the passivation layer of the semiconductor wafer. This is expensive and inefficient.
What is needed is a simpler passivation method.
A method for forming a passivation coating on a semiconductor wafer is disclosed. The method comprises: forming a silicon dioxide layer on said semiconductor wafer, said semiconductor wafer comprising a first area and a second area, said first area comprising a fuse, a semiconductor device, and an oxide layer, said oxide layer comprising a fuse window, said fuse being at a bottom of a fuse window, said second area comprising a bonding pad, said bonding pad comprising a metal layer, a spin on glass (SOG) being used in fabricating said semiconductor device; patterning and etching said silicon dioxide layer to expose said fuse window and said metal layer according to a first photomask; forming a silicon nitride layer on said silicon dioxide layer, said fuse window, and said metal layer; forming a polyimide layer on said silicon nitride layer; patterning said polyimide layer according to a second photomask; and etching said silicon nitride layer to form a spacer on a side wall of said fuse and said fuse window, and to expose said metal layer, said silicon nitride layer being etched by an anisotropic etching using said patterned polyimide layer as a mask.